The problem addressed by this invention is encountered in voltage regulation circuits. Voltage regulators are inherently medium to high gain circuits, typically greater than 50 db, with low bandwidth. With this high gain and low bandwidth, stability is often achieved by setting a dominate pole with a load capacitor. However, achieving stability over a wide range of load currents with a low value load capacitor (.about.0. 1 uF) is difficult because the load pole formed by the load capacitor and load resistor can vary by more than three decades of frequency and be as high as tens of kHz requiring the circuit to have a very broad bandwidth of greater than 3 MHz. These broad bandwidth circuits, however, are incompatible with the power IC fabrication process used to manufacture voltage regulators.
A prior art solution to the stabilization problem is illustrated in FIG. 1. The voltage regulator 2 in FIG. 1 converts an unregulated V.sub.CC voltage, 12 volts in this example, into a regulated voltage V.sub.REG, 5 volts in this example. An amplifier 6 and capacitor 12 are configured as an integrator amplifier to set the dominant pole of the system. Resistor 10 is added to provide a zero to cancel the pole of the load (load pole). The integrator amplifier drives a pass transistor 8 that provides current to the load. A feedback network including resistors 14 and 16 form a voltage divider circuit which is used to scale the output voltage such that the output voltage can be fed back to the inverting input of an error amplifier 4. The resistor 18 and capacitor 20 are not part of the voltage regulator 2 but rather are the schematic representation of the typical load on the voltage regulator circuit.
In this prior art example, the zero associated with the voltage regulator 2 can be calculated as: ##EQU1## where R=resistance of the resistor 10 and C=capacitance of the capacitor 12; and
the pole associated with the pull down resistors and load can be calculated as: ##EQU2## where RL=resistance of the load=R14 and R16 in parallel with R18. CL=is the capacitance of C20 which is typically around 0.1 microfarad.
As can be seen from the above equation, the pole associated with the prior art circuit is load (R.sub.L) dependent and can vary from 16 Hz to 32 kHz for an R14+R16 equal to 100 kilo-ohms and R18 ranging from 50 ohms to 1 mega-ohm. As will be appreciated by persons skilled in the art, the wide variation of the pole frequency is difficult to stabilize and may result in uncontrollable oscillation of the voltage regulator.
A prior art solution to this problem is to change the pull down resistors R14+R16 from 500 kilo-ohms to around 500 ohms which changes the pole frequency to a range of 3.2 kHz to 32 kHz, which is a frequency spread of 1 decade instead of 3 decades. However, the power dissipated by the pull down resistor R18 increases, as shown below: EQU power=(12v-5v)(I.sub.load+I.sub.pull down)=(7v)(100 mA)+(7 v)(10 mA)
Consequently, the 500 ohm resistor adds 70 milli-watts of power dissipation in the chip which is approximately a 10% increase in power dissipation for the added stability.
Therefore, it is desirable to provide a voltage regulator with load pole stabilization without significantly increasing power dissipation. The present invention provides this and other advantages as will be illustrated by the following description and accompanying figures.